Technical Field
Embodiments described herein relate to the field of integrated circuits and more particularly, to tracking process, voltage, and temperature variations when generating a supply voltage for a static random-access memory (SRAM) in retention mode.
Description of the Related Art
In power-efficient silicon memories, it is desirable to power a static random-access memory (SRAM) at the lowest voltage possible to minimize standby power. The SRAM bitcell is a bi-stable circuit made up of cross-coupled CMOS inverters. For an SRAM, the retention voltage defines the minimum supply voltage under which data in the SRAM is still preserved. When portions of the SRAM are not being accessed, these portions may be placed in retention mode to conserve power. In retention mode, if the voltage supplied to the SRAM cells falls below the retention voltage, the SRAM cells will fail (i.e., data stored in the SRAM cells will be lost). Therefore, it is important to provide a supply voltage which stays above the retention voltage. Unfortunately, the retention voltage is a difficult voltage to track as it varies with temperature and process. For example, as temperature decreases, the retention voltage increases. However, overcompensating and providing a supply voltage for a worst case scenario results in increased power consumption.